Abstract: The research on the preparation process and characteristics of field plates is of great significance for improving the reliability and high voltage resistance of RF LDMOS high-power devices. A field plate with a "Si substrate SiO ₂ polycrystalline titanium silicide metal" structure was prepared in the article, and the influence of its process conditions on the characteristics was analyzed and optimized. The experiment shows that PESiO ₂ with a 200nm polycrystalline dielectric layer has good BT CV stability, and the increase in annealing temperature after polycrystalline injection and titanium silicide annealing temperature is not conducive to the stability of field plate resistance and flat band voltage. Under the optimized process conditions, the field board structure has good reliability and high pressure resistance.

Keywords: titanium silicide; Field board; CV characteristics; stability

Chinese Library Classification Number: TN305.6 Document Identification Code: A Article Number: 1681-1070 (2013) 10-0033-03

A Study on Process Conditions and Properties of TiSi Field Plate

XU Shuai, XU Zheng, WU Xiaodong

(China Electronics Technology Group Corporation No.58 Research Institute, Wuxi 214035, China)

Abstract: The study of process and property of filed plate on the reliability and high voltage resistance of high power RF LDMOS device is significant In this paper, a field plate with the structure of "Si SiO ₂ - POLY - TiSi Metal" was fabricated, the effects of process conditions on properties of field plate were analyzed, and the process conditions were optimized The experience results show that, electric of PESIO ₂ with 200 nm poly have better BT CV stability, the raising of annealing temperature after poly implantation and TiSi can enhance the stability of resistance and flat belt voltage The field plate fabricated in the optimized process conditions has excellent reliability and high voltage resistance

Key words: TiSi; Field plate; CV property; Stability

1 Introduction

LDMOS (Lateral Double Diffused MOSFET) is widely used in P, L, due to its ideal switching characteristics and high breakdown voltage In S-band power devices Field plate is a commonly used terminal technology in high-voltage LDMOS design. The main purpose of adding field plate to LDMOS is to improve the breakdown voltage of the device and reduce the feedback capacitance. A field plate structure is prepared on the field oxide layer of the PN junction, which generates an electric field distribution perpendicular to the surface and works together with the electric field generated by the drain end to change the radial distribution of the power lines on the curved surface, thereby reducing the power line density and P The peak electric field intensity of the curved surface of the N junction is used to improve the withstand voltage [23].

Similar to the drift region of LDMOS, the field plate is also very sensitive to its structure and process parameters. Studying the characteristics of field board structures and optimizing their process parameters is of great significance for improving the reliability and high voltage resistance of LDMOS devices. This article studies the characteristics of a titanium silicide field plate structure and optimizes the process parameters.

Study on the Characteristics of Field Plates under Different Process Conditions

The field plate capacitor structure used in this article is Si substrate SiO ₂ polycrystalline titanium silicide metal. Based on the characteristics of this structure, analyzing the changes in capacitance characteristics, BT CV characteristics, and resistance characteristics under different process conditions can provide a deeper understanding of the internal properties of the field plate structure, thereby optimizing the process conditions and meeting the requirements of product design.

2.1 Effect of SiO2 layer preparation process and polycrystalline layer thickness on field plate CV characteristics

2.1.1 Sample preparation

Using N<100>5-9 Ω· cm as the substrate material, LPCVD and PECVD were used for SiO ₂ deposition at 100nm, followed by LPCVD polycrystalline silicon deposition at 40nm and 200nm; Then, PVD is used to deposit metal Ti, which generates titanium silicide after RTP annealing; Complete the metal deposition of Al Si Cu and etch the test pattern, and finally perform N ₂/H annealing in an oxidation furnace.

2.1.2 Testing methods

After the sample preparation is completed, the BT CV characteristics are tested using a CV tester with a temperature bias of 250 ℃, a scanning voltage of -4-3V, and a testing frequency of 1MHz.

2.1.3 Results and Analysis

Under the same testing conditions, the BT CV curve corresponding to sample c (PESiO ₂+200nm polycrystalline) exhibits stable changes in both the accumulation and inversion regions, with good patterns. Therefore, the structure of "Si substrate PESiO ₂ -200nm polycrystalline titanium silicide metal" is more stable.

2.2 Effects of polycrystalline doping annealing process and titanium silicide annealing process on field plate characteristics

2.2.1 Sample preparation

Using N<100>5-92 · cm as the substrate material, using

PECVD deposition of SiO ₂ at 200nm, followed by LPCVD polycrystalline silicon deposition at 200nm and injection of P for polycrystalline injection doping. After polycrystalline injection doping, RTP annealing is performed to activate impurities; Then, PVD is used to deposit metal Ti and generate titanium silicide after RTP annealing. After generating titanium silicide, a second annealing is carried out in RTP, followed by metal deposition of Al Si Cu and etching of test patterns. Finally, N/H annealing is carried out in an oxidation furnace.

The RTP annealing temperature after polycrystalline injection is set at different temperature points from 900 ℃ to 1000 ℃. The second annealing temperature of titanium silicide in RTP is set at different temperature points from 900 ℃ to 1000 ℃.

2.2.2 Testing methods

Test the block resistance of the samples after polycrystalline injection annealing and generating titanium silicide, and after the second annealing of titanium silicide.

After the sample preparation is completed, scan each field to read the corresponding gate voltage of 90PF and test the flat band voltage of the sample. Use a CV tester to test its BT CV characteristics, with a temperature of 250 ℃, a bias voltage of ± 35V, a scanning voltage of -10-10V, and a testing frequency of 1MHz. Use KEITHLEY to test its breakdown voltage, with a scanning voltage of 0-180V.

As the annealing temperature after injection and the annealing temperature of titanium silicide increase, the square resistance and uniformity of titanium silicide both show an increasing trend, and the changes in resistance and uniformity are stable within the range of 900~925 ℃. After the temperature rises to 950 ℃, the uniformity of the resistance increases sharply, which is not conducive to process stability. For example, when the annealing temperature of titanium silicide is 975 ℃, the uniformity of the resistance can reach up to 13%. (a: annealing after injection at 900 ℃+annealing after titanium silicide at 900 ℃; b: annealing after injection at 925 ℃+annealing after titanium silicide at 900 ℃; c: annealing after injection at 950 ℃+annealing after titanium silicide at 900 ℃; d: annealing after injection at 975 ℃+annealing after titanium silicide at 925 ℃; e: annealing after injection at 1000 ℃+annealing after titanium silicide at 925 ℃) As the annealing temperature increases, the flat band voltage and uniformity of this structure show an increasing trend, with conditions a and b having better uniformity and stability of the flat band voltage.

Therefore, under the process conditions of annealing temperature 900~925 ℃ after polycrystalline injection and 900 ℃ after titanium silicide, the resistance and flat band voltage of the titanium silicide field plate have good uniformity, which is conducive to the stability of the device.

2.3 Optimization of process conditions for titanium silicide field plate

In summary, the optimized "Si substrate SiO ₂ polycrystalline titanium silicide metal" field plate process conditions are as follows: the intermediate medium layer is PESiO ₂ and 200nm polycrystalline, the annealing temperature after polycrystalline injection is 900-925 ℃, and the annealing temperature after titanium silicide is 900 ℃.

Under a bias voltage of ± 35V, the flat band drift of the field plate structure is about ± 0.4V, which can meet the requirements of product use and has a smooth curve with high reliability.

The breakdown voltage of the 200nm PESiO ₂ dielectric prepared in this experiment is greater than 120V, indicating good high voltage resistance. Therefore, the field plate structures prepared under optimized process conditions have good reliability and high pressure resistance.

3 Conclusion

The preparation process of the "Si substrate SiO ₂ polycrystalline titanium silicide metal" field plate structure has a significant impact on its capacitance characteristics, resistance characteristics, BT CV characteristics, etc. The intermediate medium layer is PESiO, and BT CV under the condition of adding 200nm polycrystalline material has good stability. The increase in annealing temperature after polycrystalline injection and the annealing temperature of titanium silicide is not conducive to the stability of field plate resistance and flat band voltage. Under the optimized process conditions, the field plate structure has good reliability and high pressure resistance.

Reference:

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Author Introduction:

Xu Shuai (1984), male, born in Xianning, Hubei, holds a master's degree in electronic materials and devices. He is currently a process engineer at the 58th Research Institute of China Electronics Technology Group Corporation, mainly engaged in oxidation diffusion processes.